EDN

C based design methodology accelerates ASIC/FPGA design cycles

Electronic Design Automation is largely about saving time in the development of electronic designs. EDA tools strive to reduce verification time, design cycle time, and time to market. EDA is ...
EDN

Exploring new design flows — RTL synthesis

Editor's Note: In Part 2 of this series,consultant and ASIC designer Tom Moxoncovered several trends in virtual silicon prototying design flows.In this installment of the series he'll show how to link ...
Electronic Design

The ASIC Vendor's View Of RTL Rule Checking

Frequently, the customer netlists sent to ASIC vendors' design center engineers for physical implementation are riddled with problems. "If you have timing or congestion problems in implementations, it ...
Electronic Design

ASIC Handoff Gets Physical As Front And Back Ends Converge

True or false: ASIC design follows a very straightforward path that begins with high-level architectural definition. It proceeds through RTL design and preliminary floorplanning. After synthesis, the ...
Business Wire

Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced a HES-DVM™ simulation ...
Semiconductor Engineering

RTL Design-for-Power (DFP) Methodology

Commercial power analysis tools have been available now for over 10 years, operating at the gate and transistor level of abstraction. For analog, mixed-signal, and custom designs, transistor-level ...
Semiconductor Engineering

ASIC/IC Verification Trends With A Focus On Factors Of Silicon Success

At long last we come to the final installment of our four-part series presenting the findings of the Wilson Research Group Functional Verification 2020 study. In this article we discuss verification ...